Clock jitter filter

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12267043
APP PUB NO 20240333213A1
SERIAL NO

18128699

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Importance

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Abstract

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A system for reducing clock jitter may include first jitter reducing circuitry. The first jitter reducing circuitry may be arranged between an input clock signal node carrying an input clock signal and an output clock signal node carrying an output clock signal. The first jitter reducing circuitry may include a first intermediate input clock signal node and a first intermediate output clock signal node. The first jitter reducing circuitry may include a first clock delay circuit, which may be configured to: (1) delay a first intermediate input clock signal received on the first intermediate input clock signal node by an odd integer multiple of one half of a period, and (2) invert the first intermediate input clock signal. The first jitter reducing circuitry may also include a first connection, which may be from the first intermediate output clock signal node to the first intermediate input clock signal node.

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Patent Owner(s)

Patent OwnerAddress
ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANYBAY F1 RAHEEN INDUSTRIAL ESTATE CO LIMERICK LIMERICK

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Nagulapalli, Rajasekhar Northampton, GB 30 50

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Maintenance Fees

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3.5 Year Payment $1600.00 $800.00 $400.00 Oct 1, 2028
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