Adapting forward error correction (FEC) or link parameters for improved post-FEC performance

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12267210
APP PUB NO 20240214134A1
SERIAL NO

18112406

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Abstract

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Technologies for optimizing post-FEC bit error rate performance of a Forward Error Correction (FEC) system are described. A controller is coupled to an FEC circuit and a receiver circuit. The controller receives FEC symbol error data from the FEC circuit and determines, using the FEC symbol error data, a post-FEC correlated performance metric indicative of an estimated post-FEC BER of the FEC circuit. The controller adjusts, based on the post-FEC correlated performance metric, at least one of a FEC parameter of the FEC circuit or a link parameter of the receiver circuit to decrease the estimated post-FEC BER. This improves the post-FEC BER performance of the FEC circuit.

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Patent Owner(s)

Patent OwnerAddress
NVIDIA CORPORATION2701 SAN TOMAS EXPRESSWAY SANTA CLARA CA 95050

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Aziz, Pervez Mirza Dallas, US 16 213
Balan, Vishnu Saratoga, US 32 153
Rathi, Rohit Milpitas, US 13 60

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