Clocked logic gate circuit

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6316961
APP PUB NO 20010000017A1
SERIAL NO

09725812

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
RENESAS ELECTRONICS CORPORATIONTOKYO11993

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hanawa, Makoto Niiza, JP 36 446
Kaneko, Kenji Sagamihara, JP 99 1006
Kanetani, Kazuo Akishima, JP 32 189
Kusunoki, Takeshi Tachikawa, JP 22 169
Masuda, Noboru Tokorozawa, JP 58 1189
Nambu, Hiroaki Sagamihara, JP 38 275
Yamasaki, Kaname Kodaira, JP 20 97

Cited Art Landscape

Patent Info (Count) # Cites Year
 
INTEL CORPORATION (1)
* 6225826 Single ended domino compatible dual function generator circuits 11 1998
 
FREESCALE SEMICONDUCTOR, INC. (1)
5291076 Decoder/comparator and method of operation 41 1992
 
MOTOROLA, INC. (1)
5373203 Decoder and latching circuit with differential outputs 15 1993
 
SKYWORKS SOLUTIONS, INC. (1)
* 5945848 Effectively differential, multiple input OR/NOR gate architecture 7 1996
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
HITACHI ULSI SYSTEMS CO., LTD. (1)
6998878 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit 1 2004
 
INTEL CORPORATION (2)
* 6691241 Delay tuning to improve timing in multi-load systems 2 1999
* 6593778 Zero detect circuit and method for high frequency integrated circuits 1 2000
 
GOOGLE TECHNOLOGY HOLDINGS LLC (2)
* 2008/0084,777 ULTRA HIGH-SPEED NOR-TYPE LSDL/DOMINO COMBINED ADDRESS DECODER 3 2006
* 7349288 Ultra high-speed Nor-type LSDL/Domino combined address decoder 2 2006
* Cited By Examiner