Clocked logic gate circuit

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6316961
APP PUB NO 20010000017A1
SERIAL NO

09725812

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

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Patent Owner(s)

  • RENESAS ELECTRONICS CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hanawa, Makoto Niiza, JP 36 478
Kaneko, Kenji Sagamihara, JP 103 1240
Kanetani, Kazuo Akishima, JP 32 229
Kusunoki, Takeshi Tachikawa, JP 24 194
Masuda, Noboru Tokorozawa, JP 62 1348
Nambu, Hiroaki Sagamihara, JP 38 338
Yamasaki, Kaname Kodaira, JP 20 127

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