Clock generator with programmable non-overlapping-clock-edge-capability
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United States of America Patent
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Nov 27, 2001
Issued Date -
N/A
app pub date -
Dec 1, 2000
filing date -
Mar 2, 1992
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.
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