Data transfer controller, microcomputer and data processing system
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United States of America Patent
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Dec 17, 2002
Issued Date -
N/A
app pub date -
Dec 4, 2000
filing date -
Apr 16, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
A combination mode a data transfer for a transfer source and a transfer destination is previously defined by a value of resource select information of a control register (CHCRn). An address comparator circuit (SACn, DACn) has judging logic specified by the defined contents and detects, depending on its logical structure, a data transfer address error in the a data transfer controller (8) on the basis of such logical structure, in accordance with resource select information and the transfer source address and transfer destination address of the address registers (SARn, DARn). Since the data transfer is started only when the resource select information matches with the setting information of both address registers, high reliability can be assured for memory protection in the data transfer operation by the data transfer controller.
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