Step-shaped floating poly-si gate to improve a gate coupling ratio for flash memory application
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United States of America Patent
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Jan 4, 2005
Issued Date -
N/A
app pub date -
Nov 30, 2000
filing date -
Jul 6, 1999
priority date (Note) -
Expired
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Abstract
A stacked-gate flash memory cell is provided having step-shaped poly-gates with increased overlap area between them in order to increase the coupling ratio and hence the program speed of the cell. The floating gate is first formed with a step and the intergate dielectric is conformally shaped thereon followed by the forming of the control gate thereon. The increase in the-overlap area can be achieved by forming gates with multiply connected surfaces of different shapes.
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