Apparatus employable for ashing
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United States of America Patent
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Nov 27, 2001
Issued Date -
N/A
app pub date -
Dec 18, 2000
filing date -
Aug 18, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method for ashing a resist pattern covered by a hardened layer caused by an ion implantation process previously conducted including a first step for conducting an ashing process at a first temperature e.g. 120.degree. C. or less at which no popping phenomenon happens, for removing the hardened layer, and a second step for conducting an ashing process at a second temperature e.g. 150.degree. C. at which the ashing rate is high, for entirely removing the remaining resist pattern, and apparatus employable for the method for ashing a resist pattern covered by a hardened layer including a mechanism for moving up and down a semiconductor wafer to regulate the temperature of the semiconductor wafer and including a shutter which intervenes between the semiconductor wafer and a heater.
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