Method for forming a non-volatile memory cell that eliminates substrate trenching

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United States of America Patent

PATENT NO 6362050
SERIAL NO

09732381

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Abstract

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In a non-volatile memory cell that has a select transistor and a memory transistor, the substrate trenching that occurs when the gate of the select transistor and the stacked gate of the memory transistor are initially defined is eliminated by forming the gate of the select transistor and the stacked gate of the memory transistor to have substantially the same step height.

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Patent Owner(s)

Patent OwnerAddress
NATIONAL SEMICONDUCTOR CORPORATION12500 TI BOULEVARD M/S 3999 DALLAS TX 75243

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bergemont, Albert Palo Alto, CA 146 3011
Kalnitsky, Alexander San Francisco, CA 283 2681

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