Method for forming a non-volatile memory cell that eliminates substrate trenching

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6362050
SERIAL NO

09732381

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

In a non-volatile memory cell that has a select transistor and a memory transistor, the substrate trenching that occurs when the gate of the select transistor and the stacked gate of the memory transistor are initially defined is eliminated by forming the gate of the select transistor and the stacked gate of the memory transistor to have substantially the same step height.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • NATIONAL SEMICONDUCTOR CORPORATION

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bergemont, Albert Palo Alto, CA 146 2999
Kalnitsky, Alexander San Francisco, CA 269 2525

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation