Chip scale surface mount package for semiconductor device and process of fabricating the same
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United States of America Patent
Stats
-
Aug 27, 2002
Grant Date -
May 3, 2001
app pub date -
Dec 8, 2000
filing date -
Sep 13, 1999
priority date (Note) -
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Abstract
This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed. A metal layer is sputtered or evaporated on one side of the stack; the stack is turned over and a similar process is performed on the other side of the stack. The resulting metal layers are deposited on front side of the die and extend along the edges of the die to the edges and back side of the substrate. The metal is not deposited on the surfaces of the overcoat. The strips in the stack are then separated, and the saw cuts in the perpendicular direction are broken to separate the individual dice. A thick metal layer is plated on the sputtered or evaporated layers to establish a good electrical connection between the front side and the terminal on the back side of each die. The resulting package thus includes a metal layer which wraps around the edges of the die to form an electrical connection between a location on the front side of the die and the conductive substrate. The package is essentially the same size as the die. In an alternative embodiment, a nonconductive substrate is used and vias are formed in the substrate and filled with metal to make electrical contact with the terminal on the back side of the die.
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- VISHAY INTERTECHNOLOGY, INC.
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Ho, Yueh-Se | Sunnyvale, CA | 113 | 2132 |
Kasem, Y Mohammed | Santa Clara, CA | 23 | 595 |
Zandman, Felix | Bala Cynwyd, PA | 19 | 426 |
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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