Low power, high speed level shifter
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United States of America Patent
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-
Oct 23, 2001
Grant Date -
May 3, 2001
app pub date -
Dec 19, 2000
filing date -
May 10, 1995
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A voltage level translator is disclosed which translates a CMOS input signal into a CMOS output signal where the low voltage level of the output signal is equal to the high voltage level of the input signal. The voltage level translator is described in an integrated circuit such as memory circuits, including DRAMs. Specifically, the voltage level translator produces an output signal which can be used as a gate voltage on a pre-charge transistor for a booted circuit where the gate voltage need only drop to the high voltage level of the input signal to shut the transistor off. The voltage level translator described, therefore, reduces the time and power required to translate an input signal by limiting the voltage swing of the output signal.
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