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Abstract

A 64Mb DRAM includes memory cell array areas 15, sense amplifier areas 16, subword driver areas 17, and cross areas 18. For each horizontal input/output line IOH paraleel to the word line W, throuh holes on the sense amplifiers provide connections between the second metal line hierarchy M2 and the third metal line hierarchy M3. The vertical input/output line IOV parallel to the bit line BL runs through a plurality of memory cell array areas 15 in a direction parallel to the column selection signal line YS and connects to the main amplifier MA outside the memory cell array areas 15. In this input/output line configuration, the greater the number of word lines W that are selected, the greater the number of bits that can be output.

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First Claim