Semiconductor device and manufacturing method thereof

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United States of America Patent

PATENT NO 6617645
SERIAL NO

09730417

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Abstract

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An interlayer insulating film (104) that is formed on a substrate(101) so as to cover TFTs(102, 103) is planarized by mechanical polishing that is typified by CMP. Pixel electrodes (106, 107) are formed on the interlayer insulating film(104) and an insulating layer(108) is formed so as to cover the pixel electrodes. The insulating layer(108) is planarized by second mechanical polishing so that the surfaces of the pixel electrodes become flush with those of resulting buried insulating layers(112, 113). Since the pixel electrode surfaces have no steps, such problems as alignment failures of a liquid crystal material and a contrast reduction due to diffused reflection of light can be prevented.

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Patent Owner(s)

  • SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fukada, Takeshi Kanagawa, JP 70 2949
Hirakata, Yoshiharu Kanagawa, JP 491 10360
Yamazaki, Shunpei Tokyo, JP 7285 226486

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