Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit

United States of America Patent

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Mar 26, 2002
Grant Date
May 10, 2001
app pub date
Dec 22, 2000
filing date
Nov 3, 1999

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Abstract

An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles.

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Patent Owner(s)

MONTEREY RESEARCH, LLC

International Classification(s)

G11C:STATIC STORES

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[Patents Count]

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Inventor Name	Address	# of filed Patents	Total Citations
Phelan, Cathal	Mountain View, CA	2	149

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Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit

Number of patents in Portfolio can not be more than 2000

United States of America Patent

09747790

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PATENT NO	6363031
APP PUB NO	20010000995A1
SERIAL NO	09747790
DOCKET NO

US Family Size	Non-US Coverage
Patent Longevity	Forward Citations

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
March 26, 2002	US,6363031,B1 US6363031B1	GRANTED PATENT AS FIRST PUBLICATION
May 10, 2001	US,20010000995,A1 US20010000995A1	FIRST PUBLISHED PATENT APPLICATION

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09747790

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