Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions
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United States of America Patent
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Aug 12, 2003
Issued Date -
N/A
app pub date -
Jan 8, 2001
filing date -
Aug 29, 1997
priority date (Note) -
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Abstract
Processor and instruction conversion apparatus, including a technique for reducing the number of types of instructions and processor hardware scale when conditional instructions are used. The processor includes a stare hold unit, an obtaining unit, a decoding unit, a judging unit, and an execution unit. The judging unit judges whether a state hold unit renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction when decoded by the decoding unit. When the judgment is affirmative, the execution unit executes an operation specified by the operation code in the first conditional instruction decoded by the decoding unit. The instruction set is assigned first conditional instructions with a first state condition which is mutually exclusive with a second state condition for an unassigned second conditional instruction, both having the same operation code.
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