Nonvolatile semiconductor memory device structure with superimposed bit lines and short-circuit metal strips
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United States of America Patent
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Oct 23, 2001
Grant Date -
May 24, 2001
app pub date -
May 19, 1998
filing date -
May 20, 1997
priority date (Note) -
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Abstract
A nonvolatile semiconductor memory device structure having a matrix of memory cells in a semiconductor material layer. The memory cells are located at intersections of rows and columns of the matrix. Each memory cell includes a control gate electrode connected to one of the rows, a first electrode connected to one of the columns and a second electrode. The rows comprise polysilicon strips extending parallel to each other in a first direction, and the columns are formed by metal strips extending parallel to each other in a second direction orthogonal to the first direction. Short-circuit metal strips are coupled for short-circuiting the second electrodes of the memory cells. The columns and the short-circuit strips arc respectively formed in a first metal level and a second metal level superimposed on each other and electrically insulated by a dielectric layer.
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