Method for forming interconnection structure

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6287973
APP PUB NO 20010001739A1
SERIAL NO

09756242

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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In a method for forming an interconnection structure, first, second and third insulating films and a thin film are sequentially formed over lower-level metal interconnects. Then, the thin film is masked with a first resist pattern and etched to form a mask pattern with openings for interconnects. Next, the third insulating film is masked with a second resist pattern and dry-etched such that the third insulating film and the first and second resist patterns are etched at a high rate and that the second insulating film is etched at a low rate to form openings for contact holes in the third insulating film and remove the first and second resist patterns. Then, the second insulating film is masked with the third insulating film and dry-etched such that the second insulating film is etched at a high rate and that the first and third insulating films are etched at a low rate to form the openings for contact holes in the second insulating film. Then, the third and first insulating films are masked with the mask pattern and the second insulating film, respectively, and dry-etched such that the first and third insulating films are etched at a high rate and that the mask pattern and the second insulating film are etched at a low rate to form wiring grooves and contact holes in the third and first insulating films, respectively. Finally, upper-level metal interconnects and contacts are formed.

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Patent Owner(s)

  • GODO KAISHA IP BRIDGE 1;MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Aoi, Nobuo Hyogo, JP 66 902

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