Nonvolatile semiconductor memory device
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United States of America Patent
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Aug 13, 2002
Grant Date -
May 31, 2001
app pub date -
Jan 23, 2001
filing date -
May 14, 1997
priority date (Note) -
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Abstract
A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data '0' can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.
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