Programmable multi-standard I/O architecture for FPGAs
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United States of America Patent
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May 21, 2002
Issued Date -
N/A
app pub date -
Dec 18, 2000
filing date -
Dec 31, 1998
priority date (Note) -
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Abstract
The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement a large number of different output and input bus standards
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