GATE SIDEWALL PASSIVATION TO PREVENT ABNORMAL TUNGSTEN POLYCIDE GROWTH
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United States of America Patent
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Issued Date -
Jun 7, 2001
app pub date -
Nov 3, 1998
filing date -
Aug 20, 1998
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method for fabricating a semiconductor structure is provided. A WSi.sub.x (tungsten polycide) region is formed on an Si (silicon) region. At least a side surface of the WSi.sub.x region is covered with a Si liner. The Si liner is then oxidized to form an SiO.sub.2 (silicon dioxide) liner covering the side surface of the WSi.sub.x region. A semiconductor MOSFET is provided with a source, a drain, a channel region separating the source and drain and a gate. The gate includes a polycrystalline Si region, disposed over the channel region, and a WSi.sub.x gate region, disposed on the polycrystalline Si region. An oxidized SiO.sub.2 liner is provided which covers at least a side surface of the WSi.sub.x gate region. The Si liner stabilizes the WSi.sub.x region. That is, the Si liner reduces a stress in the WSi.sub.x region and reduces a production of WSi.sub.x extrusions from the WSi.sub.x region.
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