Hardened MOS transistors
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United States of America Patent
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Oct 7, 2003
Grant Date -
Jun 14, 2001
app pub date -
Dec 6, 2000
filing date -
Dec 9, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
A lateral MOS transistor including a gate and drain and source regions of a first conductivity type formed in a substrate of a second conductivity type connected to a first power supply, wherein a doped buried layer of the first conductivity type extends under said drain region and under a portion of the gate, the buried layer being connected to the gate via a one-way connection.
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