Non-volatile memory device and manufacturing process thereof
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United States of America Patent
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Issued Date -
Jun 21, 2001
app pub date -
Dec 6, 2000
filing date -
Dec 20, 1999
priority date (Note) -
Abandoned
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Abstract
A non-volatile memory device including memory cells each formed as a MOS transistor having source and drain regions and gate structures is described. The source and drain regions and the gate structures are covered by a silicon nitride layer obtained in a standard PECVD chamber at a temperature lower than 480 .degree. C. and with a suitable gas flow. An insulated layer is placed over the silicon nitride layer.
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