Flash EEPROM with on-chip erase source voltage generator
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United States of America Patent
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Nov 19, 2002
Issued Date -
N/A
app pub date -
Jan 23, 2001
filing date -
Jul 24, 1995
priority date (Note) -
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Abstract
A Flash EEPROM having negative voltage generator means for generating a negative voltage to be supplied to control gate electrodes of memory cells for erasing the memory cells. The Flash EEPROM also has first positive voltage generator means for generating a first positive voltage, independent from an external power supply of the Flash EEPROM, to be supplied to source regions of the memory cells during erasing.
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