Semiconductor memory circuit
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United States of America Patent
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-
May 21, 2002
Grant Date -
Jun 28, 2001
app pub date -
Dec 22, 2000
filing date -
Dec 27, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
A memory circuit includes a plurality of word lines connected to a plurality of memory cells, a plurality of row address decode circuits having address input terminals, a first wafer burn-in signal terminal, and a second wafer burn-in signal terminal. The row address decode circuits activate all of the word lines when the first wafer burn-in signal and the second wafer burn-in signal are in an enable state. On the other hand, the row address decode circuits activate a subset of the word lines when the second wafer burn-in signal is in the enable state.
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