Integrated circuit substrate that accommodates lattice mismatch stress
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United States of America Patent
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Aug 6, 2002
Grant Date -
Jul 5, 2001
app pub date -
Jan 29, 2001
filing date -
Dec 23, 1998
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Abstract
A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The second material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the first material by the second material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates. In the case of silicon-based substrates, the buried layer is preferably SiO.sub.2 that is sufficiently malleable at the growth temperature to allow the deformation of the isolated substrate layer.
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- 15 United States
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- 5 Korea
- 2 Other
Patent Owner(s)
- AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Chen, Yong | Mountain View, CA | 426 | 3480 |
Corzine, Scott W | Sunnyvale, CA | 57 | 1138 |
Kamins, Theodore I | Palo Alto, CA | 138 | 2895 |
Ludowise, Michael J | San Jose, CA | 20 | 1117 |
Mertz, Pierre H | Mountain View, CA | 11 | 193 |
Wang, Shih-Yuan | Palo Alto, CA | 322 | 4482 |
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