Importance

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Abstract

A semiconductor memory device, such as a SDRAM operating in a multi-bit prefetch mode, having reduced on chip noise associated with the switching of signal lines is disclosed. According to one embodiment, the semiconductor memory device may include first and second memory cell segments (201 and 202). A first Y-address buffer decoder 100-1 can be connected to the first memory cell segment 201 and a second Y-address buffer decoder 100-2 can be connected to the second memory cell segment 202. The first Y-address decoder 100-1 receives a Y-address and a first latch signal CLK1. The second Y-address decoder 100-2 receives a Y-address and a second latch signal CLK2. A clock generating circuit 400 receives an external clock signal CLK and synchronously generates the first and second latch signals (CLK1 and CLK2). The first and second latch signals (CLK1 and CLK2) are staggered with respect to each other, so as to reduce on chip noise associated with the switching of column switch lines (YSW1 and YSW2) and I/O buses (RWBS1 and RWBS2) and the activation of associated circuitry.

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First Claim