Semiconductor device and alignment method
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United States of America Patent
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-
Jan 21, 2003
Grant Date -
Jul 19, 2001
app pub date -
Jan 25, 2001
filing date -
May 4, 1998
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor wafer (101) includes a first semiconductor die (103) having a first alignment mark (165) disposed in an alignment region (163) to align the first semiconductor die on the wafer. A second semiconductor die (181) has a second alignment mark (167) disposed in the alignment region such that the second alignment mark overlaps the first alignment mark. The area occupied by the overlapping alignment marks is shared between the first and second semiconductor dice to reduce the area and the cost of each die.
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