Method of forming Self-aligned lateral DMOS with spacer drift region
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United States of America Patent
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Feb 11, 2003
Grant Date -
Jul 26, 2001
app pub date -
Feb 28, 2001
filing date -
May 18, 1998
priority date (Note) -
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Abstract
An LDMOS transistor formed in an N-type substrate. A polysilicon gate is formed atop the N-type substrate. A P-type well is formed in the N-type substrate extending from the source side to under the polysilicon gate. A N.sup.+ source region is formed in the P-type well and adjacent to the polysilicon gate. A N.sup.+ drain region is formed in the N-type substrate and in the drain side of the polysilicon gate. Finally, an N-type drift region is formed between the N.sup.+ drain region and the polysilicon gate, wherein the N-type drift region does not extend to said polysilicon gate.
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