US Patent Application No: 2001/0010,036

Number of patents in Portfolio can not be more than 2000

Logic analysis system for logic emulation systems

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Abstract

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A portion of a logic emulation system is configured to sample logic values from the portion of the emulation system that is used to emulate the user digital logic design. These sampled values are then multiplexed by the emulation system to a logic analysis device. Typically, this is a commercially-available logic analyzer. To achieve this functionality, the emulation system is provided with a clock signal that has a higher frequency than the emulation clock signal received from the target or user system. This high speed clock signal is provided to logic analyzer as a strobe signal and controls the transfer of words of logic values from the emulation system to the logic analyzer. As a result, the number of signals that the logic analyzer can effectively sample for a cycle of the emulation clock is increased. Each probe of the logic analyzer can now receive multiple time-division multiplex logic values for each emulation clock cycle thus, increasing the width of logic analysis that can be performed on a particular emulation system with the conventional logic analyzers.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
MENTOR GRAPHICS CORPORATIONWILSONVILLE, OR907

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Crouch, Kenneth Cambridge, MA 4 90
Selvidge, Charles W Wellesley, MA 24 471
Seneski, Mark Jamaica Plain, MA 10 94
Stewart, Kem Lexington, MA 3 61
Wong, Marina Wilmington, MA 3 61

Cited Art Landscape

Patent Info (Count) # Cites Year
 
FREESCALE SEMICONDUCTOR, INC. (1)
* 5,548,794 Data processor and method for providing show cycles on a fast multiplexed bus 18 1994
 
PIE DESIGNS SYSTEMS, INC. (1)
* 5,425,036 Method and apparatus for debugging reconfigurable emulation systems 259 1992
 
FUJITSU LIMITED (1)
* 5,418,452 Apparatus for testing integrated circuits using time division multiplexing 69 1993
 
QUICKTURN DESIGN SYSTEMS, INC. (1)
* 5,109,353 Apparatus for emulation of electronic hardware system 185 1988
 
MASSACHUSETTS INSTITUTE OF TECHNOLOGY (1)
* 5,596,742 Virtual interconnections for reconfigurable logic systems 213 1993
 
INTEL CORPORATION (1)
* 5,513,338 Apparatus for tracing activity on a bus of an in-circuit emulator 14 1993
 
VIRTUAL MACHINGE WORKS, INC. (1)
* 5,802,348 Logic analysis system for logic emulation systems 22 1995
 
STEP ENGINEERING, A CORP. OF CA (1)
* 4,782,461 Logical grouping of facilities within a computer development system 40 1984
 
MENTOR GRAPHICS CORPORATION (1)
* 5,659,716 Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation 52 1994
 
ACTEL CORPORATION (1)
* 4,857,774 Testing apparatus and diagnostic method for use with programmable interconnect architecture 115 1988
 
KABUSHIKI KAISHA TOSHIBA (1)
* 5,572,710 High speed logic simulation system using time division emulation suitable for large scale logic circuits 89 1993
 
NVIDIA CORPORATION (1)
* 5,680,592 System using a plurality of state machines for translating commands intended for legacy bus devices to commands for local bus devices 16 1995
 
CREDENCE SYSTEMS CORPORATION (1)
* 5,475,624 Test generation by environment emulation 75 1992
 
TEKTRONIX, INC. (1)
* 4,541,100 Apparatus including a programmable set-up and hold feature 16 1982
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
CADENCE DESIGN SYSTEMS, INC. (1)
7,739,093 Method of visualization in processor based emulation system 2 2005
 
SYNOPSYS TAIWAN CO., LTD. (1)
* 7,120,571 Resource board for emulation system 5 2003
 
MENTOR GRAPHICS CORPORATION (4)
* 7,730,353 Memory-based trigger generation scheme in an emulation environment 3 2006
8,108,729 Memory-based trigger generation scheme in an emulation environment 2 2010
8,868,974 Memory-based trigger generation scheme in an emulation environment 0 2012
8,843,861 Third party component debugging for integrated circuit design 0 2013
* Cited By Examiner