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Abstract

A sync clock signal for information reproduction is generated using a binary signal obtained from a recording medium as a reference signal. The phase of the binary signal is compared with that of the sync clock signal. A frequency is changed based on the comparison result to generate (2m+1) multi-phase clock signals mutually shifted in phase by an integral multiple of 2.pi./(2m+1). Any one of these clock signals is used as the sync clock signal for information reproduction. The binary signal is delayed by a controllable delay time to generate a binary delayed signal, the phase of which is compared with those of the clock signals. The delay time of the binary delayed signal is controlled based on the comparison result so that the level change timing of the binary delayed signal is moved on a time base away from that of the sync clock signal.

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