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Abstract

A method to planarize a flash memory device, wherein the method is applied on a substrate having a polysilicon layer and a cap layer sequentially formed thereon. Thereafter, the cap layer and the polysilicon layer are patterned to form the peripheral circuit region and the memory cell region. A dielectric layer is then formed on the substrate, covering the cap layer. A portion of the dielectric layer is further removed to expose a part of the cap layer, such that the dielectric layer above the cap layer and the dielectric layer on both sides of the cap layer become separated. A portion of the dielectric layer in the peripheral circuit region is then removed, followed by removing the cap layer, wherein the dielectric layer above the cap layer is concurrently removed to complete the planazation of the flash memory device.

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First Claim