US Patent Application No: 2001/0013,651

Number of patents in Portfolio can not be more than 2000

Semiconductor device and manufacturing method therefor

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Abstract

A semiconductor device featuring high yield and high reliability is provided. The semiconductor device includes a pad member having an electrical connection region, a passivation layer formed around the electrical connection region, and a bump electrode formed on the pad member. The bump electrode includes an electroless metal plating layer formed on the electrical connection region, and an electroless gold plating layer covering the electroless metal plating layer. The electroless gold plating layer has a thickness of 0.4 .mu.m or more.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
SEIKO EPSON CORPORATIONTOKYO16895

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Nakazawa, Fumiki Chino-shi, JP 1 5

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
SEIKO EPSON CORPORATION (2)
6,924,553 Semiconductor chip and wiring board with bumps formed on pads/land and on passivation/insulation film and manufacturing method of the same 5 2002
8,178,968 Electronic component 0 2008
 
AU OPTRONICS CORP. (1)
7,041,589 Metal bump with an insulating sidewall and method of fabricating thereof 8 2003
 
QIMONDA AG (1)
7,211,504 Process and arrangement for the selective metallization of 3D structures 0 2003
 
SPANSION LLC (1)
6,686,263 Selective formation of top memory electrode by electroless formation of conductive materials 32 2002