Importance

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Abstract

Disclosed is a synchronous type flip-flop circuit of a semiconductor device including a first clock buffer unit for buffering a complement signal of a data signal input at a first potential level of a clock signal. A second clock buffer unit buffers a complement signal of a signal output from the first clock buffer unit at the first potential level of the clock signal. A precharge latch unit precharges a first node and a second node with a supply voltage at the first potential level of the clock signal, differentially amplifying respective potentials of the first and second nodes by output signals from the first and second clock buffer units at a second potential level of the clock signal, and outputting the amplified signals while latching the amplified signals. The synchronous type flip-flop circuit of the present invention has no requirement to take into consideration problems associated with a transistor ratio. This enables a reduced circuit area and an increased operating speed.

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First Claim