Circuit for data signal recovery and clock signal regeneration
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United States of America Patent
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Aug 13, 2002
Issued Date -
N/A
app pub date -
Mar 19, 2001
filing date -
Sep 17, 1998
priority date (Note) -
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Abstract
The data and clock regeneration circuit can be completely integrated in a chip. The circuit has, in series, two independent PLL regulating stages which are optimally adjustable separately. The first PLL regulating stage has a large bandwidth and is optimized for maximum jitter tolerance and the second PLL regulating stage has a small bandwidth and is optimized for minimum jitter transfer. The circuit is suitable for use, for example, in transceivers for ATM, SONET, and SDH applications with signal transmission links in the Gbit range.
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