PLD with on-chip memory having a shadow register

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6353552
SERIAL NO

09817951

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Methods and apparatus for initializing and determining the contents of a memory block in a programmable logic device. One apparatus includes a logic element, programmably configurable to implement user-defined combinatorial or registered logic functions, and a memory block to store data. The memory block is coupled to the logic element. The memory block includes a memory storage cell to store a first data bit, a shadow cell to store a second data bit, and a transfer circuit. When a first control line of a transfer circuit is asserted, the second bit is transferred from the shadow cell to the memory storage cell. When a second control line of the transfer circuit is asserted, the first bit is transferred from the memory storage cell to the shadow cell.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • ALTERA CORPORATION;CADENCE DESIGN SYSTEMS, INC.

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Butts, Michael R Portland, OR 40 2591
Chen, Chao Chiang Cupertino, CA 6 141
Norman, Kevin A Belmont, CA 31 1330
Patel, Rakesh H Cupertino, CA 101 3031
Sample, Stephen P Saratoga, CA 39 2803

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation