Importance

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Abstract

A data processor that addresses instructions as groups of commands which may contain more than one branch command, such as VLIW instructions that contain several commands for parallel execution. The processor selects an expected taken branch command from the branch commands in a group. The processor also selects a tentative target for the expected taken branch command and tentatively redirects control flow to a further group of commands identified by the tentative target. The processor contains an associative target memory for storing targets of previously executed branch commands. Targets are retrieved with an associative address that identifies a command in the group, the tentative target being selected on the basis of a match between the associative address associated with the tentative target and an indication of the expected taken command.

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First Claim