EEPROM array using 2 bit non-volatile memory cells and method of implementing same
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United States of America Patent
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app pub date -
May 10, 2001
filing date -
Feb 4, 1999
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Abandoned
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Abstract
An electrically erasable programmable read only memory block is provided which includes a plurality of rows of 2-bit non-volatile memory cells. Each of the memory cells has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. Each pair of adjacent memory cells in each row are coupled to share a common diffusion bit line. A plurality of metal bit lines are coupled to the diffusion bit lines through high voltage select transistors. In one embodiment, there are half as many metal bit lines as diffusion bit lines.
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