Single step debug card using the PCI interface
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Jun 15, 2004
Grant Date -
Oct 4, 2001
app pub date -
Mar 14, 2001
filing date -
Mar 29, 2000
priority date (Note) -
In Force
status (Latency Note)
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Abstract
This specification discloses a single step debug card using the PCI bus, which keeps the FRAME# of the PCI bus at a low voltage; latches and displays through an LED the address and command of the PCI bus cycle; keeps the control signal of read only memory and the IRDY# ready signal and TRDY# ready signal on the PCI bus at a low voltage, latches and displays through an LED the data and byte enable of the PCI bus cycle; outputs a device selection signal from a target device when the target device is detected; intercepts the PCI bus cycle when the device selection signal is kept at a low voltage and both the IRDY# ready signal and the TRDY# ready signal are kept at a low voltage; enables the PCI host to provide a retry function when the target device cannot respond a TRDY# ready signal before the PCI bus cycle ends so as to achieve the function of single step interruption debugging.
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