Control processor dynamically loading shadow instruction register associated with memory entry of coprocessor in flexible coupling mode
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United States of America Patent
Stats
-
Mar 8, 2005
Grant Date -
Oct 18, 2001
app pub date -
Feb 23, 2001
filing date -
Feb 24, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and system are described which provide flexible coupling between a coprocessor and a control processor. The system includes a coprocessor and a system control bus connecting the coprocessor with the control processor. The coprocessor has two modes of access. In the first mode of access, the coprocessor retrieves an instruction stored in instruction memory and, in the second mode of access, the coprocessor retrieves an instruction from the control processor. The system control bus provides a path for loading an instruction to the coprocessor's shadow instruction register. The coprocessor, upon retrieving an entry in its instruction memory associated with the shadow instruction resigter, determines whether to load the instruction as an address in its program counter or to load the contents of the shadow instruction register into the instruction decode register.
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