Conflict free radiation tolerant storage cell
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Jun 3, 2003
Grant Date -
Oct 25, 2001
app pub date -
Feb 2, 2001
filing date -
Feb 4, 2000
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A Single Event Upset (SEU) resistant latch circuit that uses the Single Event Resistant Topology (SERT) comprises a first circuit module electrically coupled to a second circuit module. In the SERT-1 embodiment, the first circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. The second circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. These four output terminals satisfy a set of state equations that can be used to obtain the SERT-1 State Table. In the SERT-2 embodiment, the first circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors. The second circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors. These four output terminals satisfy a set of state equations that can be used to obtain the SERT-2 State Table.
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