Multi-bit scoreboarding to handle write-after-write hazards and eliminate bypass comparators
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United States of America Patent
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Jun 18, 2002
Grant Date -
Oct 25, 2001
app pub date -
May 31, 2001
filing date -
Apr 3, 1998
priority date (Note) -
In Force
status (Latency Note)
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Abstract
An apparatus and method of multi-bit scoreboarding to handle write-after-write hazards and eliminate bypass comparators. The method comprises providing a set of data storage units that include a set of scoreboard return path bits associated with the data storage units. The scoreboard return path bits include a set of return path indicators. A first execution unit is provided to provide an output based on an input. A first switching unit is provided to select the input to the first execution unit and to receive the output from the first execution unit. A first bypass control unit is provided to cause the first switching unit to couple the output the output from the first execution unit to the first execution unit based on the scoreboard return path bits, such that the input to the first execution unit is selected from among the data storage units and the output from the first execution unit.
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