Shared memory graphics accelerator system
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
N/A
Issued Date -
Nov 15, 2001
app pub date -
Jul 25, 2001
filing date -
Feb 4, 2000
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-chip frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.
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