Low latency shared memory switch architecture
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United States of America Patent
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Jan 21, 2003
Issued Date -
N/A
app pub date -
Dec 30, 1999
filing date -
Sep 11, 1996
priority date (Note) -
Expired
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Abstract
A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.
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