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Abstract

A logic module for a programmable logic device includes shift register circuitry in addition to the conventional programmable memory cells and look-up table decoder or selection control circuitry. In one embodiment the selection control circuitry can access either the memory cells or the various stages of the shift register. The shift register stages, and preferably the master and slave latches of each shift register stage, are accessed in a Gray code order. All of the stages of the shift register are preferably clearable in parallel. The shift registers of two logic modules are preferably cascadable to facilitate providing longer shift registers. Clock circuitry may be provided to facilitate providing two clock signals that are the logical inverse of one another with a common enable signal.

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First Claim