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Abstract

A flash memory having redundancy content addressable memory (CAM) circuitry is described. The flash memory is capable of substituting a second memory cell for an inoperative memory cell. The flash memory includes a primary array of memory cells, a redundant array of memory cells, and the redundancy CAM circuitry. The redundancy CAM circuitry includes a plurality of dual-ported CAM stages. Each CAM stage includes a CAM cell, a write data bus coupled to the CAM cell, and a read data bus coupled to the CAM cell. The CAM cell stores information regarding a location of an inoperative memory cell in the primary array. The inoperative memory cell requires a substitution with a second memory cell in the redundant array. The write data bus produces the information from the CAM cell responsively to a write select signal. The write select signal is indicative of a write operation to be performed at memory cell locations in the primary array. The read data bus produces the information from the CAM cell responsively to a read select signal. The read select signal is indicative of a read operation to be performed at memory cell locations in the primary array.

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First Claim