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Abstract

A digital delay line, which includes a plurality of multiplexer delay elements, arranged in sequence with each of the plurality of multiplexer delay elements having an associated control input. A clock signal line is coupled to a clock input of each of the plurality of multiplexers and is operative to provide synchronous, phase aligned clock signals from a clock signal source to each of said clock inputs. A control input is coupled to each of the plurality of multiplexer delay elements and is operative to transmit to each of the plurality of multiplexer delay elements an associated control signal. In response to a first change in the control signal an associated delay element is added to the delay line and in response to a second change the delay element is removed from the delay line.

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First Claim