PCI bus cycle single-step interruption debug card
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United States of America Patent
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-
Jul 5, 2005
Grant Date -
Dec 13, 2001
app pub date -
Mar 14, 2001
filing date -
Mar 29, 2000
priority date (Note) -
In Force
status (Latency Note)
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Abstract
The single-step debug card using the PCI interface according to the present invention utilizes a bus master to send out an REQ# signal to request issuing a control during the PCI bus cycle to be inspected. The address, data, command, and byte enable (BE#) of the bus cycle are locked and displayed through LEDs for single-step debugging. Through a switch circuit, a TRDY# ready signal is sent out. A device selection signal (DEVSEL#) is raised to HIGH at the same time the TRDY# ready signal finishes so as to notify the bus master on the single-step interruption debug card to end the cycle for single-step debugging.
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