Method for fabricating dual-gate structure

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20010052626A1
SERIAL NO

09938349

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Abstract

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A dual-gate semiconductor structure including a first polysilicon layer that has a p-type region and an n-type region. The p-type region overlies the channel region of a p-channel transistor, and the n-type region overlies the channel region of an n-channel transistor. A second polysilicon layer is formed directly on the first polysilicon layer, and exhibits good adhesion with the first polysilicon layer. A metal silicide layer is deposited on the second polysilicon layer. The second polysilicon layer and the metal silicide layer are deposited in different chambers of the same equipment, without breaking vacuum (i.e., in situ). The upper surface of the second polysilicon layer is therefore relatively clean, thereby providing good adhesion between the metal silicide and second polysilicon layers. The second polysilicon layer, which is either undoped or doped with nitrogen, inhibits vertical migration of impurities in the first and second regions to the overlying metal silicide layer.

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Patent Owner(s)

Patent OwnerAddress
INTEGRATED DEVICE TECHNOLOGY INC6024 SILVER CREEK VALLEY ROAD SAN JOSE CA 95138

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lo, Guo-Qiang Portland, OR 21 335

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