Apparatus for and method of controlling amplifier output offset using body biasing in MOS transistors
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 26, 2002
Grant Date -
Jan 3, 2002
app pub date -
May 24, 1999
filing date -
May 24, 1999
priority date (Note) -
In Force
status (Latency Note)
A preliminary load of PAIR data current through [] has been loaded. Any more recent PAIR data will be loaded within twenty-four hours. |
PAIR data current through []
A preliminary load of cached data will be loaded soon.
Any more recent PAIR data will be loaded within twenty-four hours.
Next PAIR Update Scheduled on [ ] |
Importance
US Family Size
|
Non-US Coverage
|
Patent Longevity
|
Forward Citations
|
Abstract
Method and apparatus for controlling amplifier output offset using body biasing in MOS transistors. A pair of input transistors have isolated bodies. A differential input signal is applied across the gates of the input transistors. An output signal is derived from a voltage at the drain of one of the input transistors. A feedback loop includes an integrator and a feedback amplifier. The integrator integrates the output signal, thereby forming an integrated output signal. The integrated output signal is applied to a first input of the feedback amplifier, while a reference voltage is applied to a second input of the feedback amplifier. The feedback amplifier controls the voltage of the body of one of the input transistors. The body of the other input transistor is coupled to its source. The threshold voltage of the input transistor having its body coupled to the feedback amplifier is controlled such that a quiescent level of the output signal tends to equal the reference voltage. A time constant associated with the feedback loop is sufficiently long that frequencies of interest for the input differential signal pass to the output of the amplifier without affecting the bias voltage formed by the feedback loop. A comparator differs from the amplifier in that the integrator and feedback amplifier are omitted and, instead, a second reference voltage is applied directly to the body of the input transistor having its body voltage controlled. The offset voltage is reduced or eliminated by adjusting the second reference voltage.
First Claim
Family
- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- SCIENCE & TECHNOLOGY CORPORATION @ UNM
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Cox, David F | Los Lunas, NM | 15 | 335 |
Cited Art Landscape
- No Cited Art to Display
Patent Citation Ranking
Forward Cite Landscape
- No Forward Cites to Display
Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
---|
Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
Full Text
Legal Events
Matter Detail
Update Public Data Dismiss Edit SaveRenewals Detail
Edit SaveNote
The template below is formatted to ensure compatibility with our system.
Provide tags with | separated like (tags1|tags2).
Maximum length is 128 characters for Customer Application No
Mandatory Fields * - 'MatterType','AppType','Country','Title','SerialNo'.
Acceptable Date Format - 'MM/DD/YYYY'.
Acceptable Filing/App Types -
- Continuation/Divisional
- Original
- Paris Convention
- PCT National
- With Priority
- EP Validation
- Provisional Conversion
- Reissue
- Provisional
- Foreign Extension
Acceptable Status -
- Pending
- Abandoned
- Unfiled
- Expired
- Granted
Acceptable Matter Types -
- Patent
- Utility Model
- Supplemental Protection Certificate
- Design
- Inventor Certificate
- Plant
- Statutory Invention Reg
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Success
E-mail has been sent successfully.
Failure
Some error occured while sending email. Please check e-mail and try again!
PAIR load has been initiated
A preliminary load of cached data will be loaded soon. Current PAIR data will be loaded within twenty four hours.
File History PDF
Thank you for your purchase! The File Wrapper for Patent Number 6362687 will be available within the next 24 hours.
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully
Important Notes on Latency of Status data
Please note there is up to 60 days of latency in this Status indicator for certain status conditions. You can obtain up-to-date Status indicator readings by ordering PAIR for the file.
An application with the status "Published" (which means it is pending) may be recently abandoned, but not yet updated to reflect its abandoned status. However, an application filed less than one year ago is unlikely to be abandoned.
A patent with the status "Granted" may be recently expired, but not yet updated to reflect its expired status. However, it is highly unlikely a patent less than 3.5 years old would be expired.
An application with the status "Abandoned" is almost always current, but there is a small chance it was recently revived and the status not yet updated.
Important Note on Priority Date data
This priority date is an estimated earliest priority date and is purely an estimation. This date should not be taken as legal conclusion. No representations are made as to the accuracy of the date listed. Please consult a legal professional before relying on this date.
We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level. Upgrade to our Level for up to -1 portfolios!.